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ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 28 features ? 184-pin registered 8-byte dual in-line memory module ? 32m/64mx72 and x64 double data rate (ddr) sdram dimm (32m x 8 sdram s ) ? performance: ? intended for 100mhz and 133mhz applications ? inputs and outputs are sstl-2 compatible ?v dd = 2.5volt 0.2, v ddq = 2.5volt 0.2 ? single pulsed ras interface ? sdrams have four internal banks for concur- rent operation ? module has one or two physical banks depend- ing on con?guration ? serial presence detect ? bi-directional data strobe with one clock cycle preamble and one-half clock post-amble ? differential clock inputs ? data is read or written on both clock edges ? address and control signals are fully synchro- nous to positive clock edge ? programmable operation: - dimm cas latency: 3, 3.5 - burst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? power down mode ? 13/10/2 addressing (row/column/bank) ? 7.8 m s max. average periodic refresh interval ? card size: 5.25" x 0.157" x 1.70" ? gold contacts ? sdram s in 66-pin tsop-ii package description this registered 184-pin double data rate (ddr) synchronous dram dual in-line memory module (dimm) can be organized as both a one- and two- bank high-speed memory array. the 32mx64/72 is a single-bank dimm that uses nine (x72) or eight (x64) 32mx8 ddr sdrams in 400 mil tsop pack- ages. the 64mx64/72 is a two-bank dimm that uses 18 (x72) or 16 (x64) 32mx8 sdrams in 400 mil tsop packages. the dimm achieves high-speed data transfer rates of up to 266mhz. the dimm is intended for use in applications oper- ating from 100mhz to 133mhz clock speeds with data rates of 200 to 266 mhz. all control and address signals are re-driven through registers to the ddr sdram devices. the control and address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge. a phase-locked loop (pll) on the dimm is used to re-drive the differential clock signals to both the ddr sdram devices and the registers, thus mini- mizing system clock loading. clock enable(s) (cke0 and/or cke1) control all devices on the dimm. prior to any access operation, the device cas latency and burst type/length/operation type must be programmed into the dimm by address inputs a0-a12 using the mode register set cycle. the dimm cas latency exceeds the sdram device spec by one clock due to the address and control signals being clocked to the sdram devices. these dimms are manufactured using raw cards developed for broad industry use by ibm as refer- ence designs. the use of these common design files will minimize electrical variation between sup- pliers. the dimm uses serial presence detects imple- mented via a serial eeprom using the two-pin iic protocol. the first 128 bytes of serial pd data are programmed and locked during module assembly. the last 128 bytes are available to the customer. all ibm 184 ddr sdram dimms provide a high- performance, flexible 8-byte interface in a 5.25 long space-saving footprint. pc200 pc266b units dimm cas latency 3 3.5 3 3.5 f ck clock frequency 100 125 125 133 mhz t ck clock cycle 10 8.0 8.0 7.5 ns f dq dq burst frequency 200 250 250 266 mhz .
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 28 19l7358.h02502 3/00 card outline pin description ck0, ck0 differential clock inputs cb0 - cb7 check bit data input/output cke0,cke1 clock enables ras row address strobe dm0 - dm8 data input mask cas column address strobe dqs0-dqs8 bidirectional data strobes we write enable v dd power (2.5v) s0, s1 chip selects v ddq supply voltage for dqs (2.5v) a0 - a9, a11, a12 address inputs v ss ground a10/ap address input/autoprecharge nc no connect ba0, ba1 sdram bank address inputs scl serial presence detect clock input reset reset pin sda serial presence detect data input/output v ref ref. voltage for sstl_2 inputs sa0-sa2 serial presence detect address inputs dq0 - dq63 data input/output v ddspd serial eeprom positive power supply (2.5 v) 1 93 52 144 53 145 92 184 (front) (back)
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 28 184-pin ddr sdram dimm pin assignments front side (left side 1 - 52, right side 53 - 92) back side (left side 93 -144, right side 145 -184) front side (left side 1 - 52, right side 53 - 92) back side (left side 93 -144, right side 145 -184) pin # x64 non-parity x72 ecc pin # x64 non-parity x72 ecc pin # x64 non-parity x72 ecc pin # x64 non-parity x72 ecc 1 vref vref 93 vss vss 48 a0 a0 140 nc dm8 2 dq0 dq0 94 dq4 dq4 49 nc cb2 141 a10 a10 3 vss vss 95 dq5 dq5 50 vss vss 142 nc cb6 4 dq1 dq1 96 vddq vddq 51 nc cb3 143 vddq vddq 5 dqs0 dqs0 97 dm0 dm0 52 ba1 ba1 144 nc cb7 6 dq2 dq2 98 dq6 dq6 key key 7 vdd vdd 99 dq7 dq7 53 dq32 dq32 145 vss vss 8 dq3 dq3 100 vss vss 54 vddq vddq 146 dq36 dq36 9 nc nc 101 nc nc 55 dq33 dq33 147 dq37 dq37 10 reset reset 102 nc nc 56 dqs4 dqs4 148 vdd vdd 11 vss vss 103 nc nc 57 dq34 dq34 149 dm4 dm4 12 dq8 dq8 104 vddq vddq 58 vss vss 150 dq38 dq38 13 dq9 dq9 105 dq12 dq12 59 ba0 ba0 151 dq39 dq39 14 dqs1 dqs1 106 dq13 dq13 60 dq35 dq35 152 vss vss 15 vddq vddq 107 dm1 dm1 61 dq40 dq40 153 dq44 dq44 16 nc nc 108 vdd vdd 62 vddq vddq 154 ras ras 17 nc nc 109 dq14 dq14 63 we we 155 dq45 dq45 18 vss vss 110 dq15 dq15 64 dq41 dq41 156 vddq vddq 19 dq10 dq10 111 cke1 cke1 65 cas cas 157 s0 s0 20 dq11 dq11 112 vddq vddq 66 vss vss 158 s1 s1 21 cke0 cke0 113 ba2 ba2 67 dqs5 dqs5 159 dm5 dm5 22 vddq vddq 114 dq20 dq20 68 dq42 dq42 160 vss vss 23 dq16 dq16 115 a12 a12 69 dq43 dq43 161 dq46 dq46 24 dq17 dq17 116 vss vss 70 vdd vdd 162 dq47 dq47 25 dqs2 dqs2 117 dq21 dq21 71 nc nc 163 nc nc 26 vss vss 118 a11 a11 72 dq48 dq48 164 vddq vddq 27 a9 a9 119 dm2 dm2 73 dq49 dq49 165 dq52 dq52 28 dq18 dq18 120 vdd vdd 74 vss vss 166 dq53 dq53 29 a7 a7 121 dq22 dq22 75 nc nc 167 nc nc 30 vddq vddq 122 a8 a8 76 nc nc 168 vdd vdd 31 dq19 dq19 123 dq23 dq23 77 vddq vddq 169 dm6 dm6 32 a5 a5 124 vss vss 78 dqs6 dqs6 170 dq54 dq54 33 dq24 dq24 125 a6 a6 79 dq50 dq50 171 dq55 dq55 34 vss vss 126 dq28 dq28 80 dq51 dq51 172 vddq vddq 35 dq25 dq25 127 dq29 dq29 81 vss vss 173 nc nc 36 dqs3 dqs3 128 vddq vddq 82 vddid vddid 174 dq60 dq60 37 a4 a4 129 dm3 dm3 83 dq56 dq56 175 dq61 dq61 38 vdd vdd 130 a3 a3 84 dq57 dq57 176 vss vss 39 dq26 dq26 131 dq30 dq30 85 vdd vdd 177 dm7 dm7 40 dq27 dq27 132 vss vss 86 dqs7 dqs7 178 dq62 dq62 41 a2 a2 133 dq31 dq31 87 dq58 dq58 179 dq63 dq63 42 vss vss 134 nc cb4 88 dq59 dq59 180 vddq vddq 43 a1 a1 135 nc cb5 89 vss vss 181 sa0 sa0 44 nc cb0 136 vddq vddq 90 nc nc 182 sa1 sa1 45 nc cb1 137 ck0 ck0 91 sda sda 183 sa2 sa2 46 vdd vdd 138 ck0 ck0 92 scl scl 184 vddspd vddspd 47 nc dqs8 139 vss vss nc = no connect; nu = not useable; du = do not use
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 28 19l7358.h02502 3/00 ordering information part number organization speed sdram cas latency leads dimension power v dd /v ddq ibm16m32644hga - 10ht 32mx64 pc200 2 gold 5.25" x 1.7" x 0.167" 2.5 v/2.5 v ibm16m32644hga - 8et pc266b 2.5 ibm16m32734hga - 10ht 32mx72 pc200 2 ibm16m32734hga - 8et pc266b 2.5 ibm16m64644hga - 10ht 64mx64 pc200 2 ibm16m64644hga - 8et pc266b 2.5 ibm16m64734hga - 10ht 64mx72 pc200 2 ibm16m64734hga - 8et pc266b 2.5
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 28 x72 ecc ddr registered sdram dimm block diagram (1 bank, x8 ddr sdrams) pck pck dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 rs0 s s s s s s s s dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dqs6 dqs7 dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 s dqs8 dqs dqs dqs dqs dqs a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v dd v ss d0-d8 d0-d8 v ddq d0- d8 d0-d8 vref notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be main- tained as shown. 3. dq/dqs resistors are 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. 5. sdram placement alternates between the back and front sides of the dimm. 6. address and control resistors are 22 ohms. v ddid strap: see note 4 ck0, ck0 --------- pll* * wire per clock loading table/wiring diagrams s0 rs0 -> s0 : sdrams d0-d8 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d8 a0-a12 ra0-ra12 -> a0-a12: sdrams d0-d8 ras rras -> ras: sdrams d0-d8 cas rcas -> cas: sdrams d0-d8 cke0 rcke0 -> cke: sdrams d0- d8 we rwe -> we: sdrams d0-d8 r e g i s t e r reset dm4 dm0 dm5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm1 dm2 dm6 dm3 dm7 dm8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 wp
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 28 19l7358.h02502 3/00 x72 ecc ddr registered sdram dimm block diagram (2 banks, x8 ddr sdrams) dm0 dqs3 dqs7 dqs2 dqs6 dqs1 dqs5 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm d9 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm d10 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm d11 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm d12 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm d13 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm d14 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dm d15 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm d16 rs0 rs1 s s s s s s s s s s s s s s s s dqs0 dqs dqs4 dqs dqs dqs dqs dqs dqs dq15 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm d8 dm d17 s s dqs8 dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs a0 serial pd a1 a2 sa0 sa1 sa2 sda v dd v ss d0-d17 d0-d17 v ddq d0-d17 d0-d17 vref notes: 1 . dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs resistors are 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. 5. rs0 and rs1 alternate between the back and front sides of the dimm. 6. address and control resistors are 22 ohms. v ddid strap: see note 4 ck0, ck0 --------- pll* * wire per clock loading table/wiring diagrams s1 rs1 -> s1 : sdrams d9-d17 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d17 a0-a12 ra0-ra12 -> a0-a12: sdrams d0-d17 ras rras -> ras: sdrams d0-d17 s0 rs0 -> s0 : sdrams d0-d8 cas rcas -> cas: sdrams d0-d17 cke0 rcke0 -> cke: sdrams d0-d8 we rwe -> we: sdrams d0-d17 r e g i s t e r pck pck reset dm1 dm3 dm4 dm5 dm7 dm6 dm8 cke1 rcke1 -> cke: sdrams d9-d17 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 scl dm2 wp
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 28 x64 ecc ddr registered sdram dimm block diagram (1 bank, x8 ddr sdrams) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm0 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 d2 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm7 rs0 s s s s s s s s dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 dqs dqs dqs dqs ck0, ck0 --------- pll* ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d7 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d7 ras rras -> ras: sdrams d0 - d7 s0 rs0 -> s0 : sdrams d0-d7 a0 serial pd a1 a2 sa0 sa1 sa2 sda * wire per clock loading table/wiring diagrams v dd v ss d0 - d7 d0 - d7 v ddq d0 - d7 d0 - d7 vref notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs/dm resistors are 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. 5. sdram placement alternates between the back and front sides of the dimm. 6. address and control resistors are 22 ohms. v ddid strap: see note 4 cas rcas -> cas: sdrams d0 - d7 cke0 rcke0 -> cke: sdrams d0 - d7 we rwe -> we: sdrams d0 - d7 r e g i s t e r pck pck /reset scl i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 wp
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 28 19l7358.h02502 3/00 x64 ecc ddr registered sdram dimm block diagram (2 banks, x8 ddr sdrams) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm d0 dm0 dm d8 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm d1 d9 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm d2 dm d10 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm d3 dm d11 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm d4 dm4 dm d12 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm d5 dm d13 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm d6 dm d14 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm d7 dm d15 dm7 rs0 rs1 s s s s s s s s s s s s s s s s dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6 dqs6 dqs7 dq15 dqs dqs dqs dqs dqs dqs dqs dqs dqs ck0, ck0 --------- pll* s1 rs1 -> s1 : sdrams d8-d15 ba0-ba1 rba0-rba1 -> ba0-ba1: sdrams d0-d15 a0-a12 ra0-ra12 -> a0-a12: sdrams d0 - d15 ras rras -> ras: sdrams d0 - d15 s0 rs0 -> s0 : sdrams d0-d7 * wire per clock loading table/wiring diagrams v dd v ss d0 - d15 d0 - d15 v ddq d0 - d15 d0 - d15 vref notes: 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. dq/dqs/dm resistors are 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. 5. rs0 and rs1 alternate between the back and front sides of the dimm. 6. address and control resistors are 22 ohms. v ddid strap: see note 4 cas rcas -> cas: sdrams d0 - d15 cke0 rcke0 -> cke: sdrams d0 - d7 we rwe -> we: sdrams d0 - d15 r e g i s t e r rcke1 -> cke: sdrams d8 - d15 pck pck cke1 reset a0 serial pd a1 a2 sa0 sa1 sa2 sda scl i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 wp
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 28 input/output functional description symbol type polarity function ck0 (sstl) positive edge the positive line of the differential pair of system clock inputs which drives the input to the on- dimm pll. all the ddr sdram addr/cntl inputs are sampled on the rising edge of their asso- ciated clocks. ck0 (sstl) negative edge the negative line of the differential pair of system clock inputs which drives the input to the on- dimm pll. cke0, cke1 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by deacti- vating the clocks, cke low initiates the power down mode, or the self refresh mode. s0, s1 (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas, we (sstl) active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. v ref supply reference voltage for sstl-2 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity ba0,1 (sstl) selects which sdram bank of four is activated. a0 - a9, a11, a12, a10/ap (sstl) during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke auto- precharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if ap is low, autoprecharge is dis- abled. during a precharge command cycle, ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 or ba1. if ap is low, ba0 and ba1 are used to define which bank to precharge. dq0 - dq63, cb0 - cb7 (sstl) data and check bit input/output pins. check bits are only applicable on the x72 dimm config- urations. dm0-dm8 (sstl) active high masks write data when high, issued concurrently with input data. both dm and dq have a write latency of one clock once the write command is registered into the sdram. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic dqs0-dqs8 (sstl) negative and posi- tive edge data strobe for input and output data reset (lvc- mos) active low asynchronously forces all register outputs low when reset is low. this signal can be used during power up to ensure cke0/1 are low and sdram dqs are hi-z. sa0 - 2 these signals are tied at the system planar to either v ss or v dd to configure the serial spd eeprom address range. sda this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pullup. scl this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to v dd to act as a pullup. v ddspd supply serial eeprom positive power supply.
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 28 19l7358.h02502 3/00 serial presence detect (part 1 of 3) byte # description spd entry value serial pd data entry (hexadecimal) notes 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram ddr 07 3 number of row addresses on assembly 13 0d 4 number of column addresses on assembly 10 0a 5 number of physical banks on dimm 32mx64, 72 1 01 64mx64, 72 2 02 6-7 data width of assembly 32m, 64mx64 x64 4000 32m, 64mx72 x72 4800 8 voltage interface level of this assembly sstl 2.5v 04 9 sdram device cycle time at maximum cl (clx = 2.5) pc200 8.0ns 80 1 pc266b 7.5ns 10 sdram device access time from clock at cl=2.5 pc200 0.8ns 80 pc266b 0.75ns 11 dimm configuration type 32m, 64mx64 non-parity 00 32m, 64mx72 ecc 02 12 refresh rate/type 7.8 m s/sr 82 13 primary sdram device width x8 08 14 error checking sdram device width x8 08 15 sdram device attributes: minimum clock delay, random col- umn access 1 clock 01 16 sdram device attributes: burst lengths supported 2, 4, 8 0e 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latency 2, 2.5 0c 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 1 02 21 sdram module attributes registered with pll, differential clock 26 22 sdram device attributes: general v dd 0.2v 00 23 minimum clock cycle at clx-0.5 (cl = 2) pc200 10.0ns a0 1 pc266b 8.0ns 80 24 maximum data access time (t ac ) from clock at clx-0.5 (cl = 2) pc200 0.8ns 80 pc266b 0.75ns 75 25 minimum clock cycle time at clx-1 (cl = 1.5) n/a 00 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. cc = checksum data byte, 00-ff (hex). 3. r = alphanumeric revision code, a-z, 0-9. 4. rr = ascii coded revision code byte r. 5. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex). 6. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex). 7. ss = serial number data byte, 00-ff (hex). 8. setup and hold values assume a 1 volt/ns slew rate.
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 28 26 maximum data access time (t ac ) from clock at clx-1 (cl = 1.5) n/a 00 27 minimum row precharge time (t rp ) 20.0ns 50 28 minimum row active to row active delay (t rrd ) 15.0ns 3c 29 minimum ras to cas delay (t rcd ) 20.0ns 50 30 minimum active to precharge time (t ras ) pc200 50.0ns 32 pc266b 45.0ns 2d 31 module bank density - 32mx64, x72 256mb 40 32 address and command setup time before clock pc200 1.2ns c0 8 pc266b 1.0ns a0 33 address and command hold time after clock pc200 1.2ns c0 pc266b 1.0ns a0 34 data/data mask input setup time before clock pc200 0.6ns 60 pc266b 1.0ns a0 35 data/data mask input hold time after clock pc200 0.6ns 60 pc266b 1.0ns a0 36-61 reserved undefined 00 62 spd revision 0 00 63 checksum for bytes 0 - 62 checksum data cc 2 64-71 manufacturers jedec id code ibm a400000000000000 72 module manufacturing location toronto, canada 91 vimercate, italy 53 73-90 module part number pc200 32mx64 ascii 16m32644hgr -10ht 31364d33323634344847rr 2d313048542020 3, 4 32mx72 ascii 16m32734hgr -10ht 31364d33323733344847rr 2d313048542020 64mx64 ascii 16m64644hgr -10ht 31364d36343634344847rr 2d313048542020 64mx72 ascii 16m64734hgr -10ht 31364d36343733344847rr 2d313048542020 pc266b 32mx64 ascii 16m32644hgr -8et 31364d33323634344847rr 2d384554202020 32mx72 ascii 16m32734hgr -8et 31364d33323733344847rr 2d384554202020 64mx64 ascii 16m64644hgr -8et 31364d36343634344847rr 2d384554202020 64mx72 ascii 16m64734hgr -8et 31364d36343733344847rr 2d384554202020 91-92 module revision code r plus ascii blank rr20 4 93-94 module manufacturing date year/week code yyww 5, 6 serial presence detect (part 2 of 3) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. cc = checksum data byte, 00-ff (hex). 3. r = alphanumeric revision code, a-z, 0-9. 4. rr = ascii coded revision code byte r. 5. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex). 6. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex). 7. ss = serial number data byte, 00-ff (hex). 8. setup and hold values assume a 1 volt/ns slew rate.
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 28 19l7358.h02502 3/00 95-98 module serial number serial number ssssssss 7 99- 127 reserved undefined 00 128- 255 open for customer use undefined 00 serial presence detect (part 3 of 3) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. cc = checksum data byte, 00-ff (hex). 3. r = alphanumeric revision code, a-z, 0-9. 4. rr = ascii coded revision code byte r. 5. ww = binary coded decimal week code, 01-52 (decimal) 01-34 (hex). 6. yy = binary coded decimal year code, 00-99 (decimal) 00-63 (hex). 7. ss = serial number data byte, 00-ff (hex). 8. setup and hold values assume a 1 volt/ns slew rate.
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 28 absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to v ss - 0.5 to v ddq + 0.5 v v in voltage on inputs relative to v ss sdram device - 0.5 to + 2.7 v serial pd device -0.3 to +6.5 v v dd voltage on v dd supply relative to v ss - 0.5 to + 2.7 v v ddq voltage on v ddq supply relative to v ss - 0.5 to + 2.7 v v ddspd voltage on v ddspd supply relative to v ss - 0.3 to +5.5 v t a operating temperature (ambient) 0 to + 70 c t stg storage temperature (plastic) - 55 to + 150 c p d power dissipation tbd w i out short circuit output current 50 ma note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operat ional sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli ability. capacitance parameter symbol max. units notes input capacitance: ck0, ck0 c i1 7pf1 input capacitance: a0-a12, ba0, ba1, we, ras, cas, cke0, cke1, so, s1 c i2 7pf1 input capacitance: reset c i3 7pf1 input capacitance: sa0-sa2, scl c i4 9pf1 input/output capacitance: dq0-63, dqs0-8, dm0-8, cb0-7 32mx64/72 c io1 10 pf 1, 2, 3 64mx64/72 c io2 15 pf input/output capacitance: sda c io3 11 pf 1. v ddq = v dd = 2.5v 0.2v, f = 100mhz, t a = 25 c, v out (dc) = v ddq/2 , vout (peak to peak) = 0.2v. 2. dm inputs are grouped with i/o pins re?ecting the fact that they are matched in loading to dq and dqs to facilitate trace matching at the board level. 3. cb0-7, dqs8 and dm8 are used on x72 dimm con?gurations only.
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 28 19l7358.h02502 3/00 electrical characteristics and dc operating conditions (0?c t a 70 c; v ddq = 2.5v 0.2v, v dd = + 2.5v 0.2v, see ac characteristics) symbol parameter min max units notes v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss , v ssq supply voltage i/o supply voltage 00v v ref i/o reference voltage 1.15 1.35 v 1, 2 v tt i/o termination voltage (system) v ref - 0.04 v ref + 0.04 v 1, 3 v ddspd supply voltage spd supply voltage 2.3 2.7 v v ih(dc) input high (logic1) voltage dq0-63, cb0-7, dqs0-8, dm0-8 v ref + 0.15 v ddq + 0.3 v1 address and control inputs v ref + 0.18 v ddq + 0.3 reset 1.7 v ddq + 0.3 v il(dc) input low (logic0) voltage dq0-63, cb0-7, dqs0-8, dm0-8 - 0.3 v ref - 0.15 v1 address and control inputs -0.3 v ref - 0.18 reset - 0.3 0.8 v in(dc) input voltage level, ck and ck inputs - 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.36 v ddq + 0.6 v 1, 4 i i input leakage current any input 0v v in v dd (all other pins not under test = 0v) address and control inputs - 55 m a1 dq0-63, cb0-7, dqs0-8, dm0-8 - 55 ck and ck - 10 10 i oz output leakage current (dqs are disabled; 0v v out v ddq dq0-63, cb0-7, dqs0-8, dm0-8 - 55 m a1 sda - 11 i oh output high current (v out = 1.95v) - 15.2 ma 1 i ol output low current (v out = 0.35v) 15.2 ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to- peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck.
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 28 ac characteristics (notes 1-5 apply to the following tables; electrical characteristics and dc operating conditions, ac operating conditions, operating, standby, and refresh currents, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. refer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still ref- erenced to v ref (or to the crossing point for ck, ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) unless otherwise specified. 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuit diagram ac operating conditions (0 ?c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage. dq0-63, cb0-7, dqs0-8, dm0-8 v ref + 0.31 v 1, 2 address and control inputs v ref + 0.35 v il(ac) input low (logic 0) voltage. dq0-63, cb0-7, dqs0-8, dm0-8 v ref - 0.31 v 1, 2 address and control inputs v ref - 0.35 v id(ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v ix(ac) input differential pair cross point voltage, ck and ck inputs (0.5*v ddq ) - 0.2 (0.5*v ddq ) + 0.2 v 1, 2, 4 f ssc ssc modulation frequency 30 50 khz d ssc 0 -.50 % 1. input slew rate = 1v/ns . 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck. 4. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 50 w timing reference point output (v out ) 30pf v tt
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 28 19l7358.h02502 3/00 operating, standby, and refresh currents (0 ?c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) symbol parameter/condition x72 x64 unit notes 2 bank 1 bank 2 bank 1 bank i dd0 operating current : one bank; active / precharge; t rc = t rc min ; t ck = t ck min ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd tbd tbd ma 1, 2 i dd1 operating current : one bank; active / read / precharge; burst = 2; t rc = t rc min ; cl = 2.5; t ck = t ck min ;i out = 0ma; address and control inputs changing once per clock cycle tbd tbd tbd tbd ma 1, 2 i dd2p precharge power-down standby current : all banks idle; power-down mode; cke v il max ; t ck = t ck min tbd tbd tbd tbd ma 1, 2 i dd2n idle standby current: cs 3 v ih min ; all banks idle; cke 3 v ih min ; t ck = t ck min ; address and control inputs changing once per clock cycle tbd tbd tbd tbd ma 1, 2 i dd3p active power-down standby current : one bank active; power-down mode; cke v il max ; t ck = t ck min tbd tbd tbd tbd ma 1, 2 i dd3n active standby current : one bank; active / precharge; cs 3 v ih min ; cke 3 v ih min ;t rc =t ras max ;t ck =t ck min ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd tbd tbd ma 1, 2 i dd4r operating current: one bank; burst = 2; reads; continu- ous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2.5; t ck = t ck min ;i out = 0ma tbd tbd tbd tbd ma 1, 2 i dd4w operating current : one bank; burst = 2; writes; continu- ous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2.5; t ck = t ck min tbd tbd tbd tbd ma 1, 2 i dd5 auto-refresh current : t rc = t rfc min tbd tbd tbd tbd ma 1, 2 i dd6 self-refresh current : cke 0.2v tbd tbd tbd tbd ma 1, 2, 3 1. i dd specifications are tested after the device is properly initialized. 2. input slew rate = 1v/ns . 3. enables on-chip refresh and address counters.
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 28 electrical characteristics & ac timing (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 1 of 3) symbol parameter pc266b pc200 unit notes min max min max t ac dq output access time from ck/ ck - 0.75 + 0.75 - 0.8 + 0.8 ns 1-4, 9 t dqsck dqs output access time from ck/ ck - 0.75 + 0.75 - 0.8 + 0.8 ns 1-4, 9 t ch ck high-level width 0.40 0.60 0.40 0.60 t ck 1, 2 t cl ck low-level width 0.40 0.60 0.40 0.60 t ck 1, 2 t ck clock cycle time dimm cl = 3.5 7.5 15 8 15 ns 1, 2 t ck dimm cl = 3.0 8 15 10 15 ns 1, 2 t dh dq and dm input hold time (to dqs) 0.5 0.6 ns 1, 3 t ds dq and dm input setup time (to dqs) 0.5 0.6 ns 1, 3 t dipw dq and dm input pulse width (each input) 1.75 2 ns 1, 3 t hz data-out high-impedance time from ck/ ck - 0.75 + 0.75 - 0.8 + 0.8 ns 1-4, 5, 9 t lz data-out low-impedance time from ck/ ck - 0.75 + 0.75 - 0.8 + 0.8 ns 1-4, 5, 9 t dqsq dqs-dq skew (dqs & associated dq signals) + 0.5 + 0.6 ns 1, 3, 4 t dqsqa dqs-dq skew (dqs & all dq signals) + 0.5 + 0.6 ns 1, 3, 4 t qh data output hold from dqs output valid time t ch/cl (min) -1.0 ns t ch/cl (min) -.75 ns ns 1, 3, 4 t dqss write command to first dqs latching transition 0.75 1.25 0.75 1.25 t ck 1, 2, 3, 9 1. input slew rate = 1v/ns 2. the ck/ ck input reference level (for timing reference to ck/ ck) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck, is v ref. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a speci?c voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the speci?c requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is de?ned as monotonic and meeting the input slew rate speci?cations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. this parameter is speci?ed at the sdram. for system-level timing analysis, the on-dimm clock skew must be included in addition to the sdram timing parameter (0.20ns). 10. this command is speci?ed at the sdram. for system-level timing analysis simulation of the dimm design ?le is highly recom- mended. this simulation will take into account dimm adders to the speci?ed values. 11. this parameter is speci?ed at the register input receiver and includes dimm-related timing adjustments. simulation with the dimm design ?le is highly recommended. 12. the time from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input sig- nal. 13. the time in which the system must maintain valid levels on the clocks and address and control signals after the reset low has been applied.
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 28 19l7358.h02502 3/00 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1, 3 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1, 2, 3, 9 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1, 2, 3, 9 t mrd mode register set command cycle time 15 16 ns 1, 2, 3 t wpres write preamble setup time 0 0 ns 1, 2, 3, 7, 9 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1, 3, 6 t wpre write preamble 0.25 0.25 t ck 1, 3 t ih address and control input hold time input slew rate >1 v/ns 0.95 0.95 ns 11 input slew rate >0.5, < 1 v/ns 1.1 1.1 t is address and control input setup time input slew rate >1 v/ns 0.95 0.95 ns 11 input slew rate >0.5, < 1 v/ns 1.1 1.1 t act register activation time 22 - 22 - ns 12 t inact register deactivation time 22 - 22 - ns 13 t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1, 3 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1, 3 electrical characteristics & ac timing (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 2 of 3) symbol parameter pc266b pc200 unit notes min max min max 1. input slew rate = 1v/ns 2. the ck/ ck input reference level (for timing reference to ck/ ck) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck, is v ref. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a speci?c voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the speci?c requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is de?ned as monotonic and meeting the input slew rate speci?cations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. this parameter is speci?ed at the sdram. for system-level timing analysis, the on-dimm clock skew must be included in addition to the sdram timing parameter (0.20ns). 10. this command is speci?ed at the sdram. for system-level timing analysis simulation of the dimm design ?le is highly recom- mended. this simulation will take into account dimm adders to the speci?ed values. 11. this parameter is speci?ed at the register input receiver and includes dimm-related timing adjustments. simulation with the dimm design ?le is highly recommended. 12. the time from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input sig- nal. 13. the time in which the system must maintain valid levels on the clocks and address and control signals after the reset low has been applied.
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 28 t ras active to precharge command 45 120,000 50 120,000 ns 1, 2, 3 t rc active to active/auto-refresh command period 65 70 ns 1, 2, 3 t rfc auto-refresh to active/auto-refresh command period 75 80 ns 1, 2, 3 t rcd active to read or write delay 20 20 ns 1, 2, 3 t rp precharge command period 20 20 ns 1, 2, 3 t rrd active bank a to active bank b command 15 15 ns 1, 2, 3 t wr write recovery time 15 15 ns 1, 2, 3 t dal auto precharge write recovery + precharge time 35 35 ns 1, 2, 3 t wtr internal write to read command delay 1 1 t ck 1, 3 t xsnr exit self-refresh to non-read command 75 80 ns 1, 3 t xsrd exit self-refresh to read command 200 200 t ck 1, 3 t refi average periodic refresh interval 7.8 7.8 m s 1, 3, 8 electrical characteristics & ac timing (0 c t a 70 c ; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 3 of 3) symbol parameter pc266b pc200 unit notes min max min max 1. input slew rate = 1v/ns 2. the ck/ ck input reference level (for timing reference to ck/ ck) is the point at which ck and ck cross: the input reference level for signals other than ck/ ck, is v ref. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a speci?c voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the speci?c requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is de?ned as monotonic and meeting the input slew rate speci?cations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. this parameter is speci?ed at the sdram. for system-level timing analysis, the on-dimm clock skew must be included in addition to the sdram timing parameter (0.20ns). 10. this command is speci?ed at the sdram. for system-level timing analysis simulation of the dimm design ?le is highly recom- mended. this simulation will take into account dimm adders to the speci?ed values. 11. this parameter is speci?ed at the register input receiver and includes dimm-related timing adjustments. simulation with the dimm design ?le is highly recommended. 12. the time from asynchronous switching of reset from low to high until the registers are stable and ready to accept an input sig- nal. 13. the time in which the system must maintain valid levels on the clocks and address and control signals after the reset low has been applied.
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 28 19l7358.h02502 3/00 wiring and topology this section contains the information needed to understand the timing relationships presented in the ac characteristics section. because the system designer must measure all signals at the first receiving device (sdram dq pin for data, register input pin for address and controls, and pll check input pin for clock), the following pages provide detailed information on these inputs. in some cases dimm timing adjustments are listed in the specifications, and in some cases it is recommended that the customer determine this informa- tion via simulation. this section enables the customer to understand the device pinouts on the dimm, the net structures, and the loading associated with these devices. for detailed timing analysis, contact an ibm mar- keting representative for simulation models. system-level modeling is strongly recommended to determine delay adders of the entire net structure in the customers application. pin assignments for the 256 mbit ddr sdram planar component (top view) 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc nc nc dq2 v ddq nc nc v dd nu nc we cas ras cs nc ba0 ba1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc nc nc dq5 v ssq dqs nc v ref v ss dm ck ck cke nc a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss 32mb x 8 x 4 bank 66-pin plastic tsop-ii 400mil
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 28 the table below describes the dq and cb wiring information for each sdram on the dimm. note that the dq wiring is different from that described in the block diagram. note: transmission lines (tl) are represented as cylinders and are labeled with length designators. these are the only lines which represent physical trace segments. for more detailed topology information please refer to the ddr sdram registered dimm design specification. sdram wiring information dq sdram designator dq sdram pin number device position to dimm tab i/o 1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 dq0 2 3 8 232432434859cb30 11203135405160cb4 dq1 5 7 12 19 28 36 47 52 63 cb7 4 15 16 27 39 44 55 56 cb5 dq2 8 2 9 222533424958cb21 10172634455061cb0 dq3 11 6 13182937465362cb65 14213038415457cb1 dq4 56 5 14213038415457cb16 13182937465362cb6 dq5 59 1 10 17 26 34 45 50 61 cb0 2 9 22 25 33 42 49 58 cb2 dq6 62 4 15162739445556cb57 12192836475263cb7 dq7 65 0 11 20 31 35 40 51 60 cb4 3 8 23 24 32 43 48 59 cb3 1. these numbers can be associated with the corresponding dimm tab pin by referencing the dimm connector pinout on pages 5 and 6 of this document. example: dq7 at the dimm tab (pin 99) is wired to sdram device position d0, pin 5 and d9, pin 62. note: 64mx72 uses ddr sdram device positions d0-d17 64mx64 uses d0-d15 only 32mx72 uses d0-d8 only 32mx64 uses d0-d7 only data, cb, dqs, and dm net structures trace lengths for data net structure tl0 tl1 tl2 total unit min max min max min max min max 0.125 0.193 0.581 0.670 0.370 0.439 1.145 1.296 inches for 2 bank dimms only tl0 dimm connector 22 w 2% tl1 tl2 sdram pin tl2 sdram pin
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 22 of 28 19l7358.h02502 3/00 the table below describes the input wiring for each clock on the dimm. clock input wiring ck0, ck0 ck1, ck1, ck2, ck2 pll clk input pin 13, 14 nc clock topology trace lengths tl0 tl1 r1 [ohms] unit 1.00 0.066 120 inches tl0 ck0 ck0 phase locked loop (pll) tl1 r1 dimm connector
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 23 of 28 the table below describes the address and control information for each signal on the dimm. note: each signal has one register input load in order to aid in system level timings. register input wiring register pin number register 1 signal register 2 signal notes 25 nc a0 26 cke1 a10 1 29 cke0 ba1 30 a12 nc 31 a11 ba0 32 a9 ras 33 a7 we 40 a8 nc 41 a5 nc 42 a6 nc 43 a4 si 1 44 a3 cas 47 a2 s0 48 a1 nc 1. cke1 and si register inputs are grounded and are nc at the dimm connector in the single bank cases. address/control signal net structure trace lengths tl0 tl1 units min max min max 0.131 0.225 0.563 0.665 inches tl0 dimm connector tl1 register 22 w
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 24 of 28 19l7358.h02502 3/00 functional description and timing diagrams refer to ibm 256mb synchronous ddr dram datasheet (document 29l0011.e36997) for functional description and timing diagrams. refer to the ibm application note power up and power management on ddr rdimms for new ddr dimm features that facilitate controlled power up and minimize power consumption.
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 25 of 28 layout drawing for 32mx64/x72 1 bank registered dimm note: all dimensions are typical unless otherwise stated. detail a millimeters inches see detail a 1.7 43.33 133.35 5.25 131.35 5.171 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 17.80 front (2) 0 3.18 .1255 3.99 .157 max. side 1.27 0.10 .050 .004 4.24 .167 4.24 .167 (front) back 6.35 .250 1.80 .071 1.27 .050 3.80 .150 4.00 .157 1.00 .039 width pitch 10.0 .394 register 1 register 2 pll d0 d2 d5 d7 d6 d4 d3 d1 d8 n/a for x64
ibm16m32644hga ibm16m64644hga ibm16m32734hga ibm16m64734hga 32/64mx64/72 1 or 2 bank registered ddr sdram module preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 26 of 28 19l7358.h02502 3/00 layout drawing for 32mx64/x72 2 bank registered dimm note: all dimensions are typical unless otherwise stated. detail a millimeters inches see detail a 1.7 43.33 133.35 5.25 131.35 5.171 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 17.80 front (2) 0 3.18 .1255 3.99 .157 max. side 1.27 0.10 .050 .004 4.24 .167 4.24 .167 (front) back 6.35 .250 1.80 .071 1.27 .050 3.80 .150 4.00 .157 1.00 .039 width pitch 10.0 .394 register 1 register 2 pll d0 d10 d2 d12 d8 d13 d5 d15 d7 d16 d6 d14 d4 d17 d3 d11 d1 d9 n/a for x64 n/a for x64
ibm16m64644hga ibm16m32644hga ibm16m64734hga ibm16m32734hga preliminary 32/64mx64/72 1 or 2 bank registered ddr sdram module 19l7358.h02502 3/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 27 of 28 revision log rev contents of modi?cation 3/00 initial release.
copyright and disclaimer copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america march 2000 the following are trademarks of international business machines corporation in the united states, or other coun- tries, or both. ibm ibm logo other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this docu- ment are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellec- tual property rights of ibm or third parties. all information contained in this document was obtained in specific environ- ments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com 19l7358.0h2502. 3/00 a

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